VHDL Design Engineer
as a team mate in Digital Chip Design Group
Your responsibilities
- VHDL coding (RTL and test benches), synthesis and verification of digital blocks used in our TOF and LiDAR sensor chips, e.g.
- Pixel and analogue operation controllers
- Sequencers
- Data stream control
- Inter block communication
- Contribute to digital design specifications
- Contribute to architectural and partitioning decisions
- Provide documentation and secure information exchange
Your skills
- Engineering background university level
- Experience in digital chip design and/or FPGA development
- Tool scripting ability, e.g. tcl, Python, is a plus
- Experience in Cadence Genus, Innovus and Modus or equivalent is a plus
- Experience in Design for Testability (DfT) for mass-production products is a plus
- Ability to communicate with all levels and other groups
- Good verbal and written language skills in English, German as an advantage
- Multi-tasking, out-of-the-box thinker, resourceful, creative and innovative
- Team player, flexible to perform in a dynamic work environment
- Honest personality and can-do spirit